1. Technical Field
Embodiments of the present invention generally relate to the delivery of power to computer processors. More particularly, embodiments relate to the protection of computer processors from voltage surges when the processor changes its current consumption from high current to low current.
2. Discussion
Mobile computing platforms such as laptop computers, or “notebook” computers, have become an integral part of modem society, and continue to grow in popularity. While the trend toward longer battery life, smaller platform size, and enhanced functionality is desirable to the consumer, it presents significant challenges to computer designers as well as manufacturers. A particular area of concern relates to the delivery of power to the central processing unit (CPU) of a mobile computing platform.
The battery life of a notebook computer is quantified as the ratio between the battery capacity and the average platform power consumption. Thus, reducing average platform power consumption increases the battery life and enhances the overall marketability of the mobile computing platform. As a result, an increasing amount of attention has been directed to developing techniques for reducing power consumption. It has been determined that portions of a typical CPU can be inactive for a relatively large percentage of the time, where applying the clock to these portions requires additional power. Typical approaches to reducing power consumption have therefore involved placing the CPU in a low-power state whenever practical by gating off the clock to unused portions of the CPU. Indeed, many notebook computer CPUs are designed with aggressive clock-gating technology.
When the unused portions of the CPU are gated off, the current demand by the CPU transitions from a relatively high value to a relatively low value, causing a condition commonly referred to as a high-to-low current consumption transient. Similarly, when the unused portions of the CPU are gated on, the current demand transitions from a relatively low value to a relatively high value, causing a condition commonly referred to as a low-to-high current consumption transient. The voltage that is supplied to the processor, however, should remain as constant as possible (staying within a tolerance window such as a ±7.5% for example) in order for the CPU to be able to function as designed. Unfortunately, the high-to-low current consumption transient tends to cause the processor voltage to surge and the low-to-high current consumption transient tends to cause the processor voltage to “droop”. Furthermore, while the droop usually may result in CPU operation failure if the voltage drops below specified limit, the surge in processor voltage constitutes a reliability degradation risk to the CPU that may manifest itself in CPU failure only after some time of operation under repetitive surges.
FIG. 1 shows one possible implementation of a conventional approach to a circuit 10 that is used to regulate the voltage applied to a CPU 26 (i.e., Vcc), where the circuit 10 uses an hysteric type of switching regulator. During constant current consumption conditions of CPU 26, the voltage at output node 16 is compared to a reference voltage, which is set to the desired voltage level (e.g., 1V) provided by a reference voltage component such as a Zener diode, bandgap reference, etc. When the voltage at output node 16 is lower than the reference voltage by −VH, a comparator 18 generates a logic high signal, causing metal oxide semiconductor field effect transistor (MOSFET) driver 30 to turn on a switching transistor (Qsw) in the power output stage 14. When Qsw is on, current in the output inductor (L), ramps up. If the voltage at output 16 is greater than the reference voltage by +VH, comparator 18 outputs a logic low signal, causing MOSFET driver 30 to turn off Qsw and turn on a synchronization transistor (QSYNC). When QSYNC is on, the current through the output inductor ramps down toward zero amps from a peak value. It should be noted that voltage regulator 12 has been simplified for discussion purposes and that inductor current ramping is a well-known phenomenon, described with the following equations.
                              v          ⁡                      (            t            )                          =                  L          ⁢                                                    ⅆ                                  i                  ⁡                                      (                    t                    )                                                                              ⅆ                t                                      .                                              Equation        ⁢                                  ⁢        1            
According to Equation 1 the inductor ramp up rate is:
                                          ⅆ                          i              ⁡                              (                t                )                                                          ⅆ            t                          =                                            V              DC                        -                          V              CC                                L                                    Equation        ⁢                                  ⁢        2            where VDC is the system voltage, and the inductor ramp down rate is:
                                          ⅆ                          i              ⁡                              (                t                )                                                          ⅆ            t                          =                                            V              CC                        L                    .                                    Equation        ⁢                                  ⁢        3            Since the system voltage (e.g., VDC) is typically on the order of 8.4-21 volts, and therefore much greater than the processor voltage, there is a much higher voltage across the output inductor during the ramp up mode than during the ramp down mode. As a result, the current ramp up rate through the inductor is substantially faster than that of the ramp down rate. Since the ramp down rate is relatively slow, the voltage surge at the output node 16 is typically greater than the voltage droop associated with the ramp up mode. The voltage surge can be estimated as follows, where VESR is the initial voltage at node 16 (VESR is not shown in the figure), and iL, is the current through inductor L.
                                          v            SURGE                    ⁡                      (            t            )                          =                                            1              C                        ⁢                          ∫                                                (                                                            i                      L                                        -                                          I                      CPU                                                        )                                ⁢                                                                  ⁢                                  ⅆ                  t                                                              +                                    V              ESR                        .                                              Equation        ⁢                                  ⁢        4            
Due to the tight space limitations associated with mobile computing platforms, a possible output decoupling that will minimize the space of the decoupling solution can achieved by using a multi-layer ceramic capacitors (MLCC) 22 connected to the output node 16, where MLCC 22 has a small form factor. Though in real application several MLCCs will be used to achieve the needed minimum total capacitance for simplicity FIG. 1 shows only one capacitor. The MLCC 22 has a relatively small equivalent series resistance (ESR), but unfortunately has a relatively low capacitance. It can be shown from Equation 4 that by using an MLCC 22 for output decoupling, VESR can be quite negligible. Due to the low capacitance, however, the voltage surge for the MLCC 22 can be significantly larger because C appears in the denominator of Equation 4. FIG. 2 shows the estimated voltage surge for a conventional power output stage in plot 24, where a 200 nH output inductor is used. In the illustrated example, the voltage surge threshold (VMAX) is exceeded due to the relatively slow ramp down rate.
One approach to reducing the voltage surge at the output node would be to reduce the inductance of the output inductor in order to increase the inductor ramp down current. There is a penalty to be paid, however, for such an approach. For example, as the inductance is reduced, there will be an increase in ripple current, which can cause an undesirably high output voltage ripple in addition to high magnetic loss in the inductor, which results in lower power-conversion efficiency. There is therefore a need to reduce the voltage surge associated with the current ramp down mode of a power output stage without negatively impacting output voltage ripple.